DDR Interface
Socionext provides various DDR interface macros from low-to-middle speed forwarding bandwidth to high-speed forwarding bandwidth or low power, with various process technologies. Moreover, we support custom SoC development by LSI-Package-Board co-design.
[DDR Interface macros]
• High-speed/ high-bandwidth : DDR3/DDR4
• Low Power : LPDDR4/LPDDR3/LPDDR2/DDR3L
• DFI compliant (all macro)
• Compatible with many different DRAM configurations and PKG options,
such as Fly-by and PoP thanks to the PHY function (training function).
• Low Power : LPDDR4/LPDDR3/LPDDR2/DDR3L
• DFI compliant (all macro)
• Compatible with many different DRAM configurations and PKG options,
such as Fly-by and PoP thanks to the PHY function (training function).
[DDR Interface design support (LSI–Package–Board co-design)]
• Timing verification : Verifies the timing of all DDR-IF systems including delays between LSI I/O and DRAM
• Power Integrity : Optimizes the parasitic inductance, resonant frequency, and power
supply (PKG, PCB) impedance as part of the power supply impedance design
• Signal Integrity : Optimizes Drivers trength, terminator resistance, and interconnect topology
• Power Integrity : Optimizes the parasitic inductance, resonant frequency, and power
supply (PKG, PCB) impedance as part of the power supply impedance design
• Signal Integrity : Optimizes Drivers trength, terminator resistance, and interconnect topology
[DDR Interface Configuration Diagram]
[LPDDR4-2400 DQ Waveforms]
Memory Controllers
Socionext provides various memory solutions for system optimization. We also offer consulting services on memory systems including memory channels and the system bus to maximize SoC performance.
Memory controller IP
• Controller for maximizing high DRAM utilization
QoS-QoS-Arbiter IP
• High performance QoS-Arbiter featuring multiple functions
Bus IP
• Original low power consumption bus with high layout flexibility
Monitor IP
• Visualizes memory system performance in real-time
• Monitors performance (bandwidth, latency) and provides an environment for tuning parameters
• Monitors performance (bandwidth, latency) and provides an environment for tuning parameters
SLVS-EC Interface
This is a high-speed interface for constructing a camera system with a high-speed, high-resolution CMOS image sensor. With a high bandwidth of up to 18.4 Gbps, this interface provides a solution for fully expressing images.
SLVS-EC Macro
SLVS-EC Macro
• Supports up to 8 times the number of lanes
• Integrates Reed-Solomon ECC
• Multiple stream transfer can be selected
• Integrates Reed-Solomon ECC
• Multiple stream transfer can be selected
10G–28Gbps SerDes Interface
With transmission performance of 10Gbps–28Gbps per channel and a configuration comprised of multiple channels, we provide a high-performance SerDes macro for constructing 100G/200G/400G optical networks or 100G Ether systems. The built-in low-jitter, high-performance PLL enables robust transmission up to 28 Gbps per channel. It also supports various standards including OIF-CEI-11GSR, OIF-CEI- 28G-SR, OIF-CEI-28G-VSR, IEEE802.3ba CAUI, IEEE802.3bm CAUI4, XFI and so forth.
Features
• x1, x4 lane configuration.• Comprised of Transmitter/Receiver/PLL and capable of bidirectional communication with 1 macro.
• Up to 112.8 Gbps per macro (for unidirectional, x4 configuration).
• Support for power-down control on each lane.
• Support for power-down control for the entire macro.
• Implementing Clock-Data recovery for each Receiver lane.
• Transmitter Equalization supported.
• Receiver Equalization supported.
• Built-in termination resistor in Transmitter/Receiver.
• Organic flip chip package (0.8 mm/1.0 mm Ball Pitch, HDBU Package).
